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I.MX27 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc |
18 / 148 page ![]() i.MX27 and i.MX27L Data Sheet, Rev. 1.5 18 Freescale Semiconductor Functional Description and Application Information • Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels • 16 simultaneous gray-scale levels from a palette of 16 for monochrome display • Support for: — Maximum resolution of 800 × 600 — Passive color panel: – 4 (mapped to RGB444)/8 (mapped to RGB444)/12 (RGB444) bits per pixel (bpp) — TFT panel: – 4 (mapped to RGB666)/8 (mapped to RGB666)/12 (RGB444)/16 (RGB565)/18 (RGB666) bpp — 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display, respectively — 16 and 256 colors out of a palette of 256 colors for 4 bpp and 8 bpp TFT display, respectively — True 4096 colors for a 12 bpp display — True 64-Kbyte colors for 16 bpp — True 256-Kbyte colors for 18 bpp — 16-bit AUO TFT LCD Panel — 24-bit AUO TFT LCD Panel 2.3.21 Multi-Master Memory Interface (M3IF)/M3IF-ESDCTL/MDDRC Interface The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the access to and from the Enhanced SDRAM/MDDR memory controller. For the other port interfaces, the M3IF only arbitrates and forwards the master requests received through the Master Port Gasket (MPG) interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that interface with the M3IF include the ARM Platform, FEC, LCDC, H.264, and the USB. The controllers are the ESDCTL/MDDRC, PCMCIA, NFC, and WEIM. 2.3.22 Multi-Layer AHB Crossbar Switch (MAX) The ARM926EJ-S processor’s instruction and data buses—and all alternate bus master interfaces—arbitrate for resources via a 6 × 34 Multi-Layer AHB Crossbar Switch (MAX). There are six (M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is uni-directional. All master and slave ports are AHB-Lite compliant. The design of the crossbar switch enables concurrent transactions to proceed from any master port to any slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three independent master requests. If a particular slave port is simultaneously requested by more than one master port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration |
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