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PIC24F04KA201 Datasheet(PDF) 123 Page - Microchip Technology |
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PIC24F04KA201 Datasheet(HTML) 123 Page - Microchip Technology |
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123 / 224 page ![]() © 2009 Microchip Technology Inc. Preliminary DS39937B-page 121 PIC24F04KA201 FAMILY bit 1 SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit not yet started, SPI1TXB is full 0 = Transmit started, SPI1TXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPI1BUF location, loading SPI1TXB. Automatically cleared in hardware when SPI1 module transfers data from SPI1TXB to SPI1SR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPI1BUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPI1 Receive Buffer Full Status bit 1 = Receive complete, SPI1RXB is full 0 = Receive is not complete, SPI1RXB is empty In Standard Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to SPI1RXB. Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR. REGISTER 15-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED) |
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