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PIC16F1934-E/ML Datasheet(PDF) 211 Page - Microchip Technology |
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PIC16F1934-E/ML Datasheet(HTML) 211 Page - Microchip Technology |
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211 / 508 page  2009 Microchip Technology Inc. Preliminary DS41364D-page 211 PIC16F193X/LF193X TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 231 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 210 CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 210 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 99 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 100 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 101 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 102 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 103 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF —CCP2IF 104 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 105 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON 201 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 202 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 197 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 197 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 132 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 137 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 140 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 143 TRISE — — — — TRISE3 TRISE2(2) TRISE1(2) TRISE0(2) 146 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Note 1: Applies to ECCP modules only. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. |
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