PIC16F1934-ESLASHML datasheet(148/508 Pages) MICROCHIP

148 / 508 page

PIC16F193X/LF193X

DS41364D-page 148

Preliminary

 2009 Microchip Technology Inc.

TABLE 12-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE(1)

U-0

R/W-1/1

U-0

—

WPUE3

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-4

Unimplemented:

Read as ‘0’

bit 3

WPUE:

Weak Pull-up Register bit

= Pull-up enabled

= Pull-up disabled

bit 2-0

Unimplemented:

Read as ‘0’

Note 1:

Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is in configured as an output.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ADCON0

—

CHS<4:0>

GO/DONE

ADON

161

ANSELE

—

ANSE2

ANSE1

ANSE0

147

CCPxCON

PxM<1:0>

DCxB<1:0>

CCPxM<3:0>

231

LATE

—

LATE3

LATE2

LATE1

LATE0

147

LCDCON

LCDEN

SLPEN

WERR

—

CS<1:0>

LMUX<1:0>

329

LCDSE2

SE23

SE22

SE21

SE20

SE19

SE18

SE17

SE16

333

PORTE

—

RE3

RE2

RE1

RE0

146

TRISE

—

TRISE3

TRISE2

TRISE1

TRISE0

146

WPUE

—

WPUE3

—

148

Legend: x

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

PORTE.

Note 1:

These registers are not implemented on the PIC16F1933/1936/1938 devices, read as ‘0’.

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