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PIC18F4580-E/ML Datasheet(PDF) 227 Page - Microchip Technology |
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PIC18F4580-E/ML Datasheet(HTML) 227 Page - Microchip Technology |
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227 / 490 page  © 2009 Microchip Technology Inc. DS39637D-page 227 PIC18F2480/2580/4480/4580 FIGURE 18-27: BUS COLLISION DURING START CONDITION (SCL = 0) FIGURE 18-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA SCL SEN bus collision occurs. Set BCLIF. SCL = 0 before SDA = 0, Set SEN, enable Start sequence if SDA = 1, SCL = 1 TBRG TBRG SDA = 0, SCL = 1 BCLIF S SSPIF Interrupt cleared in software bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, ‘0’‘0’ ‘0’ ‘0’ SDA SCL SEN Set S Set SEN, enable START sequence if SDA = 1, SCL = 1 Less than TBRG TBRG SDA = 0, SCL = 1 BCLIF S SSPIF S Interrupts cleared in software set SSPIF SDA = 0, SCL = 1, SDA pulled low by other master. Reset BRG and assert SDA. SCL pulled low after BRG time-out Set SSPIF ‘0’ |
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