PIC18F4580-ESLASHML datasheet(256/490 Pages) MICROCHIP

256 / 490 page

PIC18F2480/2580/4480/4580

DS39637D-page 256

The analog reference voltage is software-selectable to

either the device’s positive and negative supply voltage

(AVDD and AVSS), or the voltage level on the

RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.

The A/D Converter has a unique feature of being able

to operate while the device is in Sleep mode. To oper-

ate in Sleep, the A/D conversion clock must be derived

from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D Converter can be

configured as an analog input, or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH/ADRESL

registers, the GO/DONE bit (ADCON0 register) is

cleared and A/D Interrupt Flag bit, ADIF, is set. The

block diagram of the A/D module is shown in

Figure 20-1.

FIGURE 20-1:

A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

Reference

Voltage

AVDD(2)

VCFG<1:0>

CHS<3:0>

AN7(1)

AN6(1)

AN5(1)

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

10-Bit

A/D

VREF-

AVSS(2)

Converter

AN10

AN9

AN8

1010

1001

1000

Note 1: Channels, AN5 through AN7, are not available on PIC18F2X80 devices.

2: I/O pins have diode protection to VDD and VSS.

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