PIC18F4580-ESLASHML datasheet(270/490 Pages) MICROCHIP

270 / 490 page

PIC18F2480/2580/4480/4580

DS39637D-page 270

FIGURE 22-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

22.2

Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 22-1) keep CVREF from approaching the

reference source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 28.0 “Electrical Characteristics”.

22.3

Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

22.4

Effects of a Reset

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA0 pin by clearing

bit, CVROE (CVRCON<6>), and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

22.5

Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA0 pin if the

TRISA<0> bit and the CVROE bit are both set.

Enabling the voltage reference output onto the RA0

pin, with an input signal present, will increase current

consumption. Connecting RA0 as a digital output with

CVRSS

enabled

will

also

increase

current

consumption.

The RA0 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 22-2 shows an example buffering technique.

CVR<3:0>

CVREN

CVRSS = 0

VDD

VREF+

CVRSS = 1

CVRSS = 0

VREF-

CVRSS = 1

16 Steps

CVRR

CVREF

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