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PIC18F4580-E/ML Datasheet(PDF) 363 Page - Microchip Technology

Part # PIC18F4580-E/ML
Description  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
PDF  490 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4580-E/ML Datasheet(HTML) 363 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS39637D-page 363
PIC18F2480/2580/4480/4580
25.5
Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2480/2580/4480/4580
Address
Range
MEMORY SIZE/DEVICE
32 Kbytes
(PIC18F2580/4580)
16 Kbytes
(PIC18F2480/4480)
Block Code Protection
Controlled by:
BBSIZ
01
01
000000h
Boot Block
1kW
Boot Block
2kW
Boot Block
1kW
Boot Block
2kW
CPB, WRTB, EBRTB
(Boot Block)
0007FFh
000800h
Block 0
3kW
Block 0
3kW
000FFFh
001000h
Block 0
2kW
Block 0
2kW
CP0, WRT0, EBRT0
(Block 0)
001FFFh
002000h
Block 1
4kW
Block 1
4kW
Block 1
4kW
Block 1
4kW
CP!, WRT1, EBRT1
(Block 1)
003FFFh
004000h
Block 2
4kW
Block 2
4kW
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
CP2, WRT2, EBRT2
(Block 2)
005FFFh
006000h
Block 3
4kW
Block 3
4kW
CP3, WRT3, EBTR3
(Block 3)
007FFFh
008000h
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh



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