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PIC18F4580-E/ML Datasheet(PDF) 442 Page - Microchip Technology |
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PIC18F4580-E/ML Datasheet(HTML) 442 Page - Microchip Technology |
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442 / 490 page  PIC18F2480/2580/4480/4580 DS39637D-page 442 © 2009 Microchip Technology Inc. FIGURE 28-6: CLKO AND I/O TIMING TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS Param No. Symbol Characteristic Min Typ Max Units Conditions 10 TOSH2CKLOSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TOSH2CK H OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOVCLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TCKH2IOI Port In Hold after CLKO ↑ 0— — ns (Note 1) 17 TOSH2IOVOSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOIOSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) PIC18FXXXX 100 — — ns 18A PIC18LFXXXX 200 — — ns VDD = 2.0V 19 TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time) 0— — ns 20 TIOR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TIOF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx Pin High or Low Time TCY —— ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY —— ns 24† TRCP RC<7:4> Change INTx High or Low Time 20 ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. Note: Refer to Figure 28-4 for load conditions. OSC1 CLKO I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value |
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