| Electronic Components Datasheet Search |
|
PIC18F4580-E/ML Datasheet(PDF) 455 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F4580-E/ML Datasheet(HTML) 455 Page - Microchip Technology |
|
455 / 490 page ![]() © 2009 Microchip Technology Inc. DS39637D-page 455 PIC18F2480/2580/4480/4580 FIGURE 28-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 28-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 28-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 28-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V Param. No. Symbol Characteristic Min Max Units Conditions 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns 121 121 120 122 RC6/TX/CK RC7/RX/DT Pin Pin 125 126 RC6/TX/CK RC7/RX/DT Pin Pin Note: Refer to Figure 28-4 for load conditions. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |