PIC18F23K22-ESLASHML datasheet(443/492 Pages) MICROCHIP

443 / 492 page

 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 443

PIC18(L)F2X/4XK22

27.11.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 27-4:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

OSC1

CLKOUT

TABLE 27-6:

EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

FOSC

External CLKIN

Frequency(1)

MHz

EC, ECIO Oscillator mode

Oscillator Frequency(1)

MHz

RC Oscillator mode

0.1

MHz

XT Oscillator mode

MHz

HS Oscillator mode

MHz

HS + PLL Oscillator mode

200

kHz

LP Oscillator mode

1TOSC

External CLKIN Period(1)

15.6

—

EC, ECIO Oscillator mode

Oscillator Period(1)

250

—

RC Oscillator mode

250

10,000

XT Oscillator mode

62.5

250

HS Oscillator mode

HS + PLL Oscillator mode,

5200

s

LP Oscillator mode

2TCY

Instruction Cycle Time(1)

62.5

—

TCY = 4/FOSC

3TOSL,

TOSH

External Clock in (OSC1)

High or Low Time

—

XT Oscillator mode

2.5

—

s

LP Oscillator mode

—

HS Oscillator mode

4TOSR,

TOSF

External Clock in (OSC1)

Rise or Fall Time

—

XT Oscillator mode

—

LP Oscillator mode

—

7.5

HS Oscillator mode

Note 1:

Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result

in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

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