PIC18F23K22-ESLASHML datasheet(453/492 Pages) MICROCHIP

453 / 492 page

 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 453

PIC18(L)F2X/4XK22

FIGURE 27-14:

I2C™ BUS START/STOP BITS TIMING

TABLE 27-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param.

No.

Symbol

Characteristic

Min

Max

Units Conditions

TssL2scH,

TssL2scL

 to SCK  or SCK  Input

TCY

—ns

TscH

SCK Input High Time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TscL

SCK Input Low Time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

73A

Tb2b

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2

1.5 TCY + 40

—

(Note 2)

TscH2diL,

TscL2diL

Hold Time of SDI Data Input to SCK Edge

100

—

TdoR

SDO Data Output Rise Time

—

TdoF

SDO Data Output Fall Time

—

TssH2doZ

 to SDO Output High-Impedance

TscR

SCK Output Rise Time

(Master mode)

—25

TscF

SCK Output Fall Time (Master mode)

—

TscH2doV,

TscL2doV

SDO Data Output Valid after SCK Edge

—

TssL2doV

SDO Data Output Valid after SS

 Edge

—

TscH2ssH,

TscL2ssH

 after SCK Edge

1.5 TCY + 40

—

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

Note:

Refer to Figure 27-3 for load conditions.

SCL

SDA

Start

Condition

Stop

Condition

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