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PIC18F23K22-E/ML Datasheet(PDF) 459 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 459 Page - Microchip Technology |
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459 / 492 page  2010 Microchip Technology Inc. Preliminary DS41412B-page 459 PIC18(L)F2X/4XK22 FIGURE 27-20: A/D CONVERSION TIMING TABLE 27-23: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22 Param . No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bits -40°C to +85°C, VREF 2.0V A03 EIL Integral Linearity Error — ±0.5 — LSb -40°C to +85°C, VREF 2.0V A04 EDL Differential Linearity Error — ±0.4 — LSb -40°C to +85°C, VREF 2.0V A06 EOFF Offset Error — 0.4 — LSb -40°C to +85°C, VREF 2.0V A07 EGN Gain Error — 0.3 — LSb -40°C to +85°C, VREF 2.0V A08 ETOTL Total Error — 1 — LSb -40°C to +85°C, VREF 2.0V A20 VREF Reference Voltage Range (VREFH – VREFL) 1.8 2.0 — — — — V V Absolute Minimum Minimum for 1LSb Accuracy A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL —VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source —— 3 k -40°C to +85°C Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (Note 2) 98 7 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. .. . . . . TCY |
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