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PIC18F23K22-E/ML Datasheet(PDF) 482 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 482 Page - Microchip Technology |
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482 / 492 page  PIC18(L)F2X/4XK22 DS41412B-page 482 Preliminary 2010 Microchip Technology Inc. Reception ......................................................... 286 Transmission .................................................... 283 Synchronous Slave Mode Associated Registers, Receive ........................ 290 Reception ......................................................... 290 Transmission .................................................... 288 Extended Instruction Set ADDFSR .................................................................. 410 ADDULNK ................................................................ 410 and Using MPLAB Tools .......................................... 416 CALLW ..................................................................... 411 Considerations for Use ............................................ 414 MOVSF .................................................................... 411 MOVSS .................................................................... 412 PUSHL ..................................................................... 412 SUBFSR .................................................................. 413 SUBULNK ................................................................ 413 Syntax ...................................................................... 409 F Fail-Safe Clock Monitor .............................................. 44, 349 Fail-Safe Condition Clearing ...................................... 44 Fail-Safe Detection .................................................... 44 Fail-Safe Operation .................................................... 44 Reset or Wake-up from Sleep .................................... 44 Fast Register Stack ............................................................ 72 Fixed Voltage Reference (FVR) Associated Registers ............................................... 338 Flash Program Memory ...................................................... 95 Associated Registers ............................................... 103 Control Registers ....................................................... 96 EECON1 and EECON2 ..................................... 96 TABLAT (Table Latch) Register ......................... 98 TBLPTR (Table Pointer) Register ...................... 98 Erase Sequence ...................................................... 100 Erasing ..................................................................... 100 Operation During Code-Protect ............................... 103 Reading ...................................................................... 99 Table Pointer Boundaries Based on Operation ........................ 98 Table Pointer Boundaries .......................................... 98 Table Reads and Table Writes .................................. 95 Write Sequence ....................................................... 101 Writing To ................................................................. 101 Protection Against Spurious Writes ................. 103 Unexpected Termination .................................. 103 Write Verify ...................................................... 103 G GOTO ............................................................................... 388 H Hardware Multiplier .......................................................... 111 Introduction .............................................................. 111 Operation ................................................................. 111 Performance Comparison ........................................ 111 High/Low-Voltage Detect ................................................. 343 Applications .............................................................. 346 Associated Registers ............................................... 347 Characteristics ......................................................... 440 Current Consumption ............................................... 345 Effects of a Reset ..................................................... 347 Operation ................................................................. 344 During Sleep .................................................... 347 Setup ........................................................................ 345 Start-up Time ........................................................... 345 Typical Low-Voltage Detect Application .................. 346 HLVD. See High/Low-Voltage Detect. ............................. 343 I I2C Mode (MSSPx) Acknowledge Sequence Timing .............................. 246 Bus Collision During a Repeated Start Condition .................. 251 During a Stop Condition .................................. 252 Effects of a Reset .................................................... 247 I2C Clock Rate w/BRG ............................................. 254 Master Mode Operation ......................................................... 238 Reception ........................................................ 244 Start Condition Timing ............................. 240, 241 Transmission ................................................... 242 Multi-Master Communication, Bus Collision and Arbitration ........................................................ 248 Multi-Master Mode ................................................... 247 Read/Write Bit Information (R/W Bit) ....................... 223 Slave Mode Transmission ................................................... 228 Sleep Operation ....................................................... 247 Stop Condition Timing ............................................. 246 ID Locations ............................................................. 349, 365 INCF ................................................................................ 388 INCFSZ ............................................................................ 389 In-Circuit Debugger .......................................................... 365 In-Circuit Serial Programming (ICSP) ...................... 349, 365 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 414 Indexed Literal Offset Mode ............................................. 414 Indirect Addressing ............................................................ 91 INFSNZ ............................................................................ 389 Instruction Cycle ................................................................ 74 Clocking Scheme ....................................................... 74 Instruction Flow/Pipelining ................................................. 74 Instruction Set .................................................................. 367 ADDLW .................................................................... 373 ADDWF .................................................................... 373 ADDWF (Indexed Literal Offset Mode) .................... 415 ADDWFC ................................................................. 374 ANDLW .................................................................... 374 ANDWF .................................................................... 375 BC ............................................................................ 375 BCF ......................................................................... 376 BN ............................................................................ 376 BNC ......................................................................... 377 BNN ......................................................................... 377 BNOV ...................................................................... 378 BNZ ......................................................................... 378 BOV ......................................................................... 381 BRA ......................................................................... 379 BSF .......................................................................... 379 BSF (Indexed Literal Offset Mode) .......................... 415 BTFSC ..................................................................... 380 BTFSS ..................................................................... 380 BTG ......................................................................... 381 BZ ............................................................................ 382 CALL ........................................................................ 382 CLRF ....................................................................... 383 CLRWDT ................................................................. 383 COMF ...................................................................... 384 CPFSEQ .................................................................. 384 CPFSGT .................................................................. 385 CPFSLT ................................................................... 385 |
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