PC312XDP512F0CFVR datasheet(967/1348 Pages) FREESCALE

967 / 1348 page

Figure 23-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)

Figure 23-78. Pulse Illustration

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by

4 consecutive samples of an active level directly or indirectly.

The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock

is generated by an RC-oscillator in the port integration module. To maximize current saving the

RC oscillator runs only if the following condition is true on any pin individually:

Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).

23.0.9

Expanded Bus Pin Functions

All peripheral ports T, S, M, P, H, J, AD0, and AD1 start up as general purpose inputs after reset.

Depending on the external mode pin condition, the external bus interface related ports A, B, C, D,

E, and K start up as general purpose inputs on reset or are configured for their alternate functions.

Table 23-69. Pulse Detection Criteria

Pulse

Mode

STOP

Unit

STOP1

1. These values include the spread of the oscillator frequency over

temperature, voltage and process.

Ignored

tpulse ≤ 3

Bus clocks

tpulse ≤ tpign

Uncertain

3 < tpulse < 4

Bus clocks

tpign < tpulse < tpval

Valid

tpulse ≥ 4

Bus clocks

tpulse ≥ tpval

Glitch, ﬁltered out, no interrupt ﬂag set

Valid pulse, interrupt ﬂag set

tpign

tpval

uncertain

tpulse

PC312XDP512F0CFVR Datasheet(PDF) 967 Page - Freescale Semiconductor, Inc