PC312XDP512F0CFVR datasheet(1154/1348 Pages) FREESCALE

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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)

MC9S12XDP512 Data Sheet, Rev. 2.21

1156

Freescale Semiconductor

MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.

The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When

writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.

28.3.2.4

Flash Conﬁguration Register (FCNFG)

The FCNFG register enables the Flash interrupts and gates the security backdoor writes.

76543210

MRDS

00000

Reset

00000000

= Unimplemented or Reserved

Figure 28-6. Flash Test Mode Register (FTSTMOD —Normal Mode)

76543210

MRDS

WRALL

0000

Reset

00000000

= Unimplemented or Reserved

Figure 28-7. Flash Test Mode Register (FTSTMOD — Special Mode)

Table 28-6. FTSTMOD Field Descriptions

Field

Description

6:5

MRDS[1:0]

Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash

array as shown in Table 28-7.

WRALL

Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register

address will be written simultaneously during a register write.

0 Write only to the FDATA register bank selected using BKSEL.

1 Write to all FDATA register banks.

Table 28-7. FTSTMOD Margin Read Settings

MRDS[1:0]

Margin Read Setting

Normal

Program Margin1

1 Flash array reads will be sensitive to program margin.

Erase Margin2

2 Flash array reads will be sensitive to erase margin.

Normal

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