PC912XDP512F0CALR datasheet(135/1348 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

135

4.3.2.4

ATD Control Register 3 (ATDCTL3)

This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze

Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.

Read: Anytime

Write: Anytime

76543210

S8C

S4C

S2C

S1C

FIFO

FRZ1

FRZ0

Reset

00100000

= Unimplemented or Reserved

Figure 4-6. ATD Control Register 3 (ATDCTL3)

Table 4-8. ATDCTL3 Field Descriptions

Field

Description

S8C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S4C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S2C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S1C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

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