910GL datasheet(202/426 Pages) INTEL

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Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

202

Datasheet

10.1.24

PMCS—Power Management Control/Status (D2:F1)

PCI Device:

Address Offset:

D4h

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

Bit

Access &

Default

Description

0 b

PME_Status: This bit is 0 to indicate that IGD does not support PME# generation

from D3 (cold).

14:9

Reserved

0 b

PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.

7:2

Reserved

1:0

R/W

00 b

Power State: This field indicates the current power state of the IGD and can be

used to set the IGD into a new power state. If software attempts to write an

unsupported state to this field, write operation must complete normally on the

bus, but the data is discarded and no state change occurs.

On a transition from D3 to D0 the graphics controller is optionally reset to initial

values. Behavior of the graphics controller in supported states is detailed in the

power management section.

00 = D0 (Default)

01 = D1 (Not Supported)

10 = D2 (Not Supported)

11 = D3

10.1.25

SWSMI—Software SMI (D2:F1)

PCI Device:

Address Offset:

E0h

Default Value:

0000h

Access:

R/W

Size:

16 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

910GL Datasheet(PDF) 202 Page - Intel Corporation

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