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910GL Datasheet(PDF) 399 Page - Intel Corporation

Part # 910GL
Description  Express Chipset
PDF  426 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

910GL Datasheet(HTML) 399 Page - Intel Corporation

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Testability
R
Datasheet
399
15
Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been
implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin
connected to it.
15.1
Complimentary Pins
Table 15-1 contains pins which must remain complimentary while performing XOR testing. The
first and third columns contain the pin and its compliment. The second and fourth columns
specify which chain the associated pins are on.
Note:
The SDQSx# pins are only used in DDR2 mode. In DDR it is not necessary to drive
SDQS_A[7:0]# or SDQS_B[7:0]#.
Table 15-1. Complimentary Pins to Drive
Complimentary Pin
XOR Chain
Complimentary Pin
XOR Chain
HDSTBP0#
FSB XOR 1
H_DSTBN0#
FSB XOR 1
HDSTBP1#
FSB XOR 0
HDSTBN1#
FSB XOR 0
HDSTBP2#
FSB XOR 0
HDSTBN2#
FSB XOR 0
HDSTBP3#
FSB XOR 0
HDSTBN3#
FSB XOR 0
SDQS_A0
SM XOR 6
SDQS_A0#
SM XOR 4
SDQS_A1
SM XOR 6
SDQS_A1#
SM XOR 4
SDQS_A2
SM XOR 6
SDQS_A2#
SM XOR 4
SDQS_A3
SM XOR 4
SDQS_A3#
SM XOR 6
SDQS_A4
SM XOR 4
SDQS_A4
SM XOR 2
SDQS_A5
SM XOR 2
SDQS_A5#
SM XOR 4
SDQS_A6
SM XOR 2
SDQS_A6#
SM XOR 4
SDQS_A7
SM XOR 2
SDQS_A7#
SM XOR 4
SDQS_A8
SM XOR 2
SDQS_A8#
SM XOR 4
SDQS_B0
SM XOR 7
SDQS_B0#
SM XOR 5
SDQS_B1
SM XOR 7
SDQS_B1#
SM XOR 5
SDQS_B2
SM XOR 7
SDQS_B2#
SM XOR 5
SDQS_B3
SM XOR 7
SDQS_B3#
SM XOR 5
SDQS_B4
SM XOR 7
SDQS_B4#
SM XOR 5
SDQS_B5
SM XOR 3
SDQS_B5#
SM XOR 5
SDQS_B6
SM XOR 3
SDQS_B6#
SM XOR 5
SDQS_B7
SM XOR 3
SDQS_B7#
SM XOR 5
SDQS_B8
SM XOR 7
SDQS_B8#
SM XOR 5



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