ST10F272Z2T3 datasheet(180/189 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272Z2

180/189

25.8.19

External bus arbitration

VDD = 5 V

± 10%, V

SS = 0 V, TA = -40 to +125 °C, CL = 50 pF

Partially tested, guaranteed by design characterization.

Figure 62.

External bus arbitration (releasing the bus)

The ST10F272Z2 will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to become active.

The CS outputs will be resistive high (pull-up) after t64.

Table 82.

External bus arbitration timings

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64 MHz

min.

max.

min.

max.

t61

HOLD input setup time

to CLKOUT

18.5–18.5–

t62

CLKOUT to HLDA high

or BREQ low delay

–

12.5

–

12.5

t63

CLKOUT to HLDA low

or BREQ high delay

–

12.5

–

12.5

t64

CSx release 1)

–20

–

t65

CSx drive

– 415– 415

t66

Other signals release 1)

–20

–

t67

Other signals drive

– 4

t61

t63

t66

t64

t62

CLKOUT

HOLD

HLDA

BREQ

Others

CSx

(P6.x)

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