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TMS320F2812 Datasheet(PDF) 122 Page - Texas Instruments

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Part # TMS320F2812
Description  Digital Signal Processors
PDF  170 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2812 Datasheet(HTML) 122 Page - Texas Instruments

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SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
SPISTE
(A)
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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-28. SPI Slave Mode External Timing (Clock Phase = 0)
122
Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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