PIC24FV32KA302-ISLASHML datasheet(210/364 Pages) MICROCHIP

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PIC24FV32KA304 FAMILY

DS39995D-page 210

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22.1

A/D Control Registers

The 12-bit A/D Converter module uses up to

43 registers for its operation. All registers are mapped

in the data memory space.

22.1.1

CONTROL REGISTERS

Depending on the specific device, the module has up to

eleven control and status registers:

• AD1CON1: A/D Control Register 1

• AD1CON2: A/D Control Register 2

• AD1CON3: A/D Control Register 3

• AD1CON5: A/D Control Register 5

• AD1CHS: A/D Sample Select Register

• AD1CHITH and AD1CHITL: A/D Scan Compare

Hit Registers

• AD1CSSL and AD1CSSH: A/D Input Scan Select

Registers

• AD1CTMUENH and AD1CTMUENL: CTMU

Enable Registers

The AD1CON1, AD1CON2 and AD1CON3 registers

(Register 22-1,

and

control the overall operation of the A/D module. This

includes enabling the module, configuring the

conversion clock and voltage reference sources,

selecting the sampling and conversion triggers, and

manually controlling the sample/convert sequences.

The AD1CON5 register (Register 22-4) specifically

controls features of the Threshold Detect operation,

including its function in power-saving modes.

The AD1CHS register (Register 22-5) selects the input

channels to be connected to the S/H amplifier. It also

allows the choice of input multiplexers and the

selection of a reference source for differential

sampling.

The

AD1CHITH

and

AD1CHITL

registers

(Register 22-6 and Register 22-7) are semaphore

registers used with Threshold Detect operations. The

status of individual bits, or bit pairs in some cases,

indicate if a match condition has occurred. AD1CHITL

is always implemented, whereas AD1CHITH may not

be implemented in devices with 16 or fewer channels.

The

AD1CSSH/L

registers

(Register 22-8

and

sequential scanning.

The AD1CTMUENH/L registers (Register 22-10 and

CTMU during conversions. Selecting a particular

channel allows the A/D Converter to control the CTMU

(particularly, its current source) and read its data

through that channel. AD1CTMUENL is always

implemented, whereas AD1CTMUENH may not be

implemented in devices with 16 or fewer channels.

22.1.2

A/D RESULT BUFFERS

The module incorporates a multi-word, dual port RAM,

called ADC1BUF. The buffer is composed of at least

the same number of word locations as there are

external analog channels for a particular device, with a

maximum number of 32. The number of buffer

addresses is always even. Each of the locations is

mapped into the data memory space and is separately

addressable. The buffer locations are referred to as

ADC1BUF0 through ADC1BUFn (up to 31).

The A/D result buffers are both readable and writable.

When the module is active (AD1CON<15> = 1), the

buffers are read-only, and store the results of A/D

conversions.

When

the

module

inactive

(AD1CON<15> = 0), the buffers are both readable and

writable. In this state, writing to a buffer location

programs a conversion threshold for Threshold Detect

operations.

Buffer contents are not cleared when the module is

deactivated with the ADON bit (AD1CON1<15>).

Conversion results and any programmed threshold

values are maintained when ADON is set or cleared.

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