PIC18F2525IP datasheet(266/412 Pages) MICROCHIP

266 / 412 page

PIC18F2525/2620/4525/4620

DS39626E-page 264

23.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPx bits have no direct

effect. CPx bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTx Configuration bit is ‘0’. The EBTRx

bits control table reads. For a block of user memory

with the EBTRx bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will result

in reading ‘0’s. Figures 23-6 through 23-8 illustrate table

write and table read protection.

FIGURE 23-6:

TABLE WRITE (WRTx) DISALLOWED

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP operation or an

external programmer.

000000h

0007FFh

000800h

003FFFh

004000h

007FFFh

008000h

00BFFFh

00C000h

00FFFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLWT*

TBLPTR = 0008FFh

PC = 003FFEh

TBLWT*

PC = 00BFFEh

Program Memory

Configuration Bit Settings

Results: All table writes disabled to Blockn whenever WRTx = 0.

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