DSPIC33FJMC202ESS datasheet(202/330 Pages) MICROCHIP

202 / 330 page

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-page 202

FIGURE 20-3:

ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

20.3

ADC Helpful Tips

The SMPI<3:0> (AD1CON2<5:2>) control bits:

a) Determine when the ADC interrupt flag is

set and an interrupt is generated if enabled.

b) When the CSCNA bit (AD1CON2<10>) is

set to ‘1’, determines when the ADC analog

scan

channel

list

defined

the

AD1CSSL/AD1CSSH registers starts over

from the beginning.

On devices without a DMA peripheral,

determines when ADC result buffer pointer

to ADC1BUF0-ADC1BUFF, gets reset back

to the beginning at ADC1BUF0.

On devices without a DMA module, the ADC has

16 result buffers. ADC conversion results are

stored sequentially in ADC1BUF0-ADC1BUFF

regardless of which analog inputs are being

used

subject

the

SMPI<3:0>

bits

(AD1CON2<5:2>) and the condition described

in 1c above. There is no relationship between

the ANx input being measured and which ADC

buffer

(ADC1BUF0-ADC1BUFF)

that

the

conversion results will be placed in.

On devices with a DMA module, the ADC mod-

ule has only 1 ADC result buffer, (i.e.,

ADC1BUF0), per ADC peripheral and the ADC

conversion result must be read either by the

CPU or DMA controller before the next ADC

conversion is complete to avoid overwriting the

previous value.

The DONE bit (AD1CON1<0>) is only cleared at

the start of each conversion and is set at the

completion of the conversion, but remains set

indefinitely even through the next sample phase

until the next conversion begins. If application

code is monitoring the DONE bit in any kind of

software loop, the user must consider this

behavior because the CPU code execution is

faster than the ADC. As a result, in manual sam-

ple mode, particularly where the users code is

setting the SAMP bit (AD1CON1<1>), the

DONE bit should also be cleared by the user

application just before setting the SAMP bit.

On devices with two ADC modules, the

ADCxPCFG registers for both ADC modules

must be set to a logic ‘1’ to configure a target

I/O pin as a digital I/O pin. Failure to do so

means that any alternate digital input function

will always see only a logic ‘0’ as the digital

input buffer is held in Disable mode.

20.4

ADC Resources

Many useful resources are provided on the main prod-

uct page of the Microchip web site for the devices listed

in this data sheet. This product page, which can be

accessed using this link, contains the latest updates

and additional information.

20.4.1

KEY RESOURCES

• Section 16. “Analog-to-Digital Converter

(ADC)” (DS70183)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference

Manuals Sections

• Development Tools

ADC Internal

RC Clock(2)

TOSC(1)

ADC Conversion

Clock Multiplier

1, 2, 3, 4, 5,..., 64

AD1CON3<15>

TCY

TAD

AD1CON3<5:0>

Note 1: Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal

to the clock frequency. TOSC = 1/FOSC.

2: See the ADC Electrical Characteristics for the exact RC clock value.

Note:

In the event you are not able to access

the product page using the link above,

enter

this

URL

your

browser:

http://www.microchip.com/wwwproducts/

Devices.aspx?dDocName=en530334

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