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DSPIC33FJMC202ESS Datasheet(PDF) 271 Page - Microchip Technology |
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DSPIC33FJMC202ESS Datasheet(HTML) 271 Page - Microchip Technology |
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271 / 330 page  © 2007-2012 Microchip Technology Inc. DS70283K-page 271 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Param No. Symbol Characteristic(3) Min(1) Max Units Conditions IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs— 400 kHz mode TCY/2 (BRG + 1) — μs— 1 MHz mode(2) TCY/2 (BRG + 1) — μs— IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs— 400 kHz mode TCY/2 (BRG + 1) — μs— 1 MHz mode(2) TCY/2 (BRG + 1) — μs— IM20 TF:SCL SDAx and SCLx Fall Time 100 kHz mode — 300 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx Rise Time 100 kHz mode — 1000 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns — 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input Hold Time 100 kHz mode 0 — μs— 400 kHz mode 0 0.9 μs 1 MHz mode(2) 0.2 — μs IM30 TSU:STA Start Condition Setup Time 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for Repeated Start condition 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM31 THD:STA Start Condition Hold Time 100 kHz mode TCY/2 (BRG + 1) — μs After this period the first clock pulse is generated 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM33 TSU:STO Stop Condition Setup Time 100 kHz mode TCY/2 (BRG + 1) — μs— 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns — Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid From Clock 100 kHz mode — 3500 ns — 400 kHz mode — 1000 ns — 1 MHz mode(2) — 400 ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free before a new transmission can start 400 kHz mode 1.3 — μs 1 MHz mode(2) 0.5 — μs IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 4 Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: These parameters are characterized by similarity, but are not tested in manufacturing. 4: Typical value for this parameter is 130 ns. |
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