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DSPIC33FJMC202ESS Datasheet(PDF) 323 Page - Microchip Technology |
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DSPIC33FJMC202ESS Datasheet(HTML) 323 Page - Microchip Technology |
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323 / 330 page  © 2007-2012 Microchip Technology Inc. DS70283K-page 323 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AD1CSSL (ADC1 Input Scan Select Low)................ 210 AD1PCFGL (ADC1 Port Configuration Low) ............ 210 CLKDIV (Clock Divisor)............................................. 107 CORCON (Core Control) ...................................... 23, 75 DFLTCON (QEI Control)........................................... 177 I2CxCON (I2Cx Control) ........................................... 188 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 192 I2CxSTAT (I2Cx Status) ........................................... 190 ICxCON (Input Capture x Control) ............................ 153 IEC0 (Interrupt Enable Control 0) ............................... 84 IEC1 (Interrupt Enable Control 1) ............................... 86 IEC3 (Interrupt Enable Control 3) ............................... 87 IEC4 (Interrupt Enable Control 4) ............................... 88 IFS0 (Interrupt Flag Status 0) ..................................... 79 IFS1 (Interrupt Flag Status 1) ..................................... 81 IFS3 (Interrupt Flag Status 3) ..................................... 82 IFS4 (Interrupt Flag Status 4) ..................................... 83 INTCON1 (Interrupt Control 1).................................... 76 INTCON2 (Interrupt Control 2).................................... 78 INTTREG Interrupt Control and Status Register......... 99 IPC0 (Interrupt Priority Control 0) ............................... 89 IPC1 (Interrupt Priority Control 1) ............................... 90 IPC14 (Interrupt Priority Control 14) ........................... 96 IPC15 (Interrupt Priority Control 15) ........................... 97 IPC16 (Interrupt Priority Control 16) ........................... 97 IPC18 (Interrupt Priority Control 18) ........................... 98 IPC2 (Interrupt Priority Control 2) ............................... 91 IPC3 (Interrupt Priority Control 3) ............................... 92 IPC4 (Interrupt Priority Control 4) ............................... 93 IPC5 (Interrupt Priority Control 5) ............................... 94 IPC7 (Interrupt Priority Control 7) ............................... 95 NVMCON (Flash Memory Control) ............................. 57 NVMKEY (Nonvolatile Memory Key) .......................... 58 OCxCON (Output Compare x Control) ..................... 158 OSCCON (Oscillator Control) ................................... 105 OSCTUN (FRC Oscillator Tuning) ............................ 109 P1DC2 (PWM Duty Cycle 2)..................................... 172 P1DC3 (PWM Duty Cycle 3)..................................... 172 PDC1 (PWM Duty Cycle 1)....................................... 172 PLLFBD (PLL Feedback Divisor).............................. 108 PMD1 (Peripheral Module Disable Control Register 1) ........................................................ 114 PMD1 (Peripheral Module Disable Control Register 1) .. 114 PMD2 (Peripheral Module Disable Control Register 2) ........................................................ 115 PMD3 (Peripheral Module Disable Control Register 3) ........................................................ 116 PMD3 (Peripheral Module Disable Control Register 3) .. 116 PTCON (PWM Time Base Control) .......................... 163 PTMR (PWM Timer Count Value)............................. 164 PTPER (PWM Time Base Period) ............................ 164 PWMxCON1 (PWM Control 1).................................. 166 PWMxCON2 (PWM Control 2).................................. 167 PxDTCON1 (Dead-Time Control 1) .......................... 168 PxDTCON2 (Dead-Time Control 2) .......................... 169 PxFLTACON (Fault A Control).................................. 170 PxOVDCON (Override Control) ................................ 171 PxSECMP (Special Event Compare)........................ 165 QEICON (QEI Control).............................................. 175 RCON (Reset Control) ................................................ 63 SPIxCON1 (SPIx Control 1)...................................... 182 SPIxCON2 (SPIx Control 2)...................................... 184 SPIxSTAT (SPIx Status and Control) ....................... 181 SR (CPU Status)................................................... 21, 75 T1CON (Timer1 Control) .......................................... 145 T2CON Control)........................................................ 149 T3CON Control......................................................... 150 UxMODE (UARTx Mode) ......................................... 195 UxSTA (UARTx Status and Control) ........................ 197 Reset Illegal Opcode....................................................... 61, 69 Trap Conflict ......................................................... 68, 69 Uninitialized W Register ....................................... 61, 69 Reset Sequence ................................................................. 71 Resets ................................................................................ 61 S Serial Peripheral Interface (SPI)....................................... 179 Software Reset Instruction (SWR)...................................... 68 Software Simulator (MPLAB SIM) .................................... 229 Software Stack Pointer, Frame Pointer CALLL Stack Frame ................................................... 46 Special Features of the CPU ............................................ 211 SPI Module SPI1 Register Map ..................................................... 39 Symbols Used in Opcode Descriptions ............................ 220 System Control Register Map .............................................................. 44 T Temperature and Voltage Specifications AC..................................................................... 244, 285 Timer1 .............................................................................. 143 Timer2/3 ........................................................................... 147 Timing Characteristics CLKO and I/O ........................................................... 247 Timing Diagrams 10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)......................... 278 10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)....................................... 278 12-bit ADC Conversion (ASAM = 0, SSRC<2:0> = 000) ........................................... 277 Brown-out Situations .................................................. 68 External Clock .......................................................... 245 I2Cx Bus Data (Master Mode) .................................. 270 I2Cx Bus Data (Slave Mode) .................................... 272 I2Cx Bus Start/Stop Bits (Master Mode)................... 270 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 272 Input Capture (CAPx) ............................................... 253 Motor Control PWM .................................................. 255 Motor Control PWM Fault ......................................... 255 OC/PWM .................................................................. 254 Output Compare (OCx) ............................................ 253 QEA/QEB Input ........................................................ 256 QEI Module Index Pulse........................................... 257 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer......................................... 248 Timer1, 2, 3 External Clock ...................................... 250 TimerQ (QEI Module) External Clock ....................... 252 Timing Requirements ADC Conversion (10-bit mode) ................................ 290 ADC Conversion (12-bit Mode) ................................ 290 CLKO and I/O ........................................................... 247 External Clock .......................................................... 245 Input Capture............................................................ 253 SPIx Master Mode (CKE = 0) ................................... 286 SPIx Module Master Mode (CKE = 1) ...................... 286 SPIx Module Slave Mode (CKE = 0) ........................ 287 |
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