PIC18F1220ESLASHPQTP datasheet(108/308 Pages) MICROCHIP

108 / 308 page

PIC18F1220/1320

DS39605F-page 106

12.3

Timer1 Oscillator Layout

Considerations

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in output compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single sided PCB, or in addition to a ground plane.

FIGURE 12-4:

OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

12.4

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow,

which is

latched in interrupt

flag

bit, TMR1IF

(PIR1<0>). This interrupt can be enabled/disabled by

setting/clearing Timer1 Interrupt Enable bit, TMR1IE

(PIE1<0>).

12.5

Resetting Timer1 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode

to generate

“special

event

trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer1 and start an A/D conversion, if the A/D mod-

ule is enabled (see Section 15.4.4 “Special Event

Trigger” for more information).

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPR1H:CCPR1L regis-

ter pair effectively becomes the period register for

Timer1.

12.6

Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see

Figure 12-2).

When

the

RD16

control

bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, is

valid, due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

RA1

RA4

RB0

MCLR

VSS

RA2

RA3

Note: Not drawn to scale.

RA3

RB2

OSC1

RB5

OSC2

VDD

RB7

RB6

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit,

TMR1IF (PIR1<0>).

PIC18F1220E/PQTP Datasheet(PDF) 108 Page - Microchip Technology

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