PIC18F1220ESLASHPQTP datasheet(131/308 Pages) MICROCHIP

131 / 308 page

DS39605F-page 129

PIC18F1220/1320

15.5.9

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCP1 module for PWM operation:

Configure the PWM pins P1A and P1B (and

P1C and P1D, if used) as inputs by setting the

corresponding TRISB bits.

Set the PWM period by loading the PR2 register.

Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

• Select one of the available output

configurations and direction with the

P1M1:P1M0 bits.

• Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

Set the PWM duty cycle by loading the CCPR1L

For Half-Bridge Output mode, set the dead-

band delay by loading PWM1CON<6:0> with

the appropriate value.

If auto-shutdown operation is required, load the

ECCPAS register:

• Select the auto-shutdown sources using the

ECCPAS<2:0> bits.

• Select the shutdown states of the PWM

output pins using PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

• Set the ECCPASE bit (ECCPAS<7>).

If auto-restart operation is required, set the

PRSEN bit (PWM1CON<7>).

Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

Enable PWM outputs after a new PWM cycle

has started:

• Wait until TMR2 overflows (TMR2IF bit is set).

• Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRISB

bits.

• Clear the ECCPASE bit (ECCPAS<7>).

15.5.10

OPERATION IN LOW-POWER

MODES

In the Low-Power Sleep mode, all clock sources are

disabled. Timer2 will not increment and the state of the

module will not change. If the ECCP pin is driving a

value, it will continue to drive that value. When the

device wakes up, it will continue from this state. If Two-

Speed Start-ups are enabled, the initial start-up

frequency may not be stable if the INTOSC is being

used.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change.

In all other low-power modes, the selected low-power

mode clock will clock Timer2. Other low-power mode

clocks will most likely be different than the primary

clock frequency.

15.5.10.1

Operation with Fail-Safe

Clock Monitor

the

Fail-Safe

Clock

Monitor

enabled

(CONFIG1H<6> is programmed), a clock failure will

force the device into the Low-Power RC_RUN mode

and the OSCFIF bit (PIR2<7>) will be set. The ECCP

will then be clocked from the INTRC clock source,

which may have a different clock frequency than the

primary clock. By loading the IRCF2:IRCF0 bits on

Resets, the user can enable the INTOSC at a high

clock speed in the event of a clock failure.

See the previous section for additional details.

15.5.11

EFFECTS OF A RESET

Both power-on and subsequent Resets will force all

ports to input mode and the CCP registers to their

Reset states.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

PIC18F1220E/PQTP Datasheet(PDF) 131 Page - Microchip Technology

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