PIC18F2610ESLASHSOSQTP datasheet(246/376 Pages) MICROCHIP

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PIC18F2X1X/4X1X

DS39636D-page 248

22.2

Watchdog Timer (WDT)

For PIC18F2X1X/4X1X devices, the WDT is driven by

the INTRC source. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period

is 4 ms and has the same stability as the INTRC

oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in Configu-

ration Register 2H. Available periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

postscaler are cleared when any of the following events

occur: a SLEEP or CLRWDT instruction is executed, the

IRCF bits (OSCCON<6:4>) are changed or a clock

failure has occurred.

22.2.1

CONTROL REGISTER

readable and writable register which contains a control

bit that allows software to override the WDT Configura-

tion bit, but only if the Configuration bit has disabled the

WDT.

FIGURE 22-1:

WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

3: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

INTRC Source

WDT

Wake-up From

Reset

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

Sleep

÷128

Change on IRCF bits

Modes

PIC18F2610E/SOSQTP Datasheet(PDF) 246 Page - Microchip Technology

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