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PIC18F2610E/SOSQTP Datasheet(PDF) 337 Page - Microchip Technology |
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PIC18F2610E/SOSQTP Datasheet(HTML) 337 Page - Microchip Technology |
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337 / 376 page ![]() © 2009 Microchip Technology Inc. DS39636D-page 339 PIC18F2X1X/4X1X FIGURE 25-12: PARALLEL SLAVE PORT TIMING (PIC18F4410/4415/4510/4515/4610) TABLE 25-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4410/4415/4510/4515/4610) Note: Refer to Figure 25-5 for load conditions. RE2/CS RE0/RD RE1/WR RD7:RD0 62 63 64 65 Param. No. Symbol Characteristic Min Max Units Conditions 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In Invalid (hold time) PIC18FXXXX 20 — ns PIC18LFXXXX 35 — ns VDD = 2.0V 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ —3 TCY |
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