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PIC18F2610E/SOSQTP Datasheet(PDF) 365 Page - Microchip Technology |
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PIC18F2610E/SOSQTP Datasheet(HTML) 365 Page - Microchip Technology |
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365 / 376 page  © 2009 Microchip Technology Inc. DS39636D-page 367 PIC18F2X1X/4X1X Direct Addressing ............................................................... 72 E Effect on Standard PIC Instructions ........................... 73, 306 Effects of Power Managed Modes on Various Clock Sources 33 Electrical Characteristics .................................................. 313 Enhanced Capture/Compare/PWM (ECCP) .................... 139 Capture and Compare Modes .................................. 140 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ....................................... 140 Pin Configurations for ECCP1 ................................. 140 PWM Mode. See PWM (ECCP Module). Standard PWM Mode ............................................... 140 Timer Resources ...................................................... 140 Enhanced PWM Mode. See PWM (ECCP Module). ........ 141 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 218 A/D Minimum Charging Time ................................... 218 Errata ................................................................................... 8 EUSART Asynchronous Mode ................................................ 202 12-Bit Break Transmit and Receive ................. 207 Associated Registers, Receive ........................ 205 Associated Registers, Transmit ....................... 203 Auto-Wake-up on Sync Break ......................... 206 Receiver ........................................................... 204 Setting up 9-bit Mode with Address Detect ...... 204 Transmitter ....................................................... 202 Baud Rate Generator Operation in Power Managed Mode ................ 197 Baud Rate Generator (BRG) .................................... 197 Associated Registers ....................................... 197 Auto-Baud Rate Detect .................................... 200 Baud Rate Error, Calculating ........................... 197 Baud Rates, Asynchronous Modes ................. 198 High Baud Rate Select (BRGH Bit) ................. 197 Sampling .......................................................... 197 Synchronous Master Mode ...................................... 208 Associated Registers, Receive ........................ 210 Associated Registers, Transmit ....................... 209 Reception ......................................................... 210 Transmission ................................................... 208 Synchronous Slave Mode ........................................ 211 Associated Registers, Receive ........................ 212 Associated Registers, Transmit ....................... 211 Reception ......................................................... 212 Transmission ................................................... 211 Extended Instruction Set .................................................. 301 ADDFSR .................................................................. 302 ADDULNK ................................................................ 302 and Using MPLAB Tools .......................................... 308 CALLW ..................................................................... 303 Considerations for Use ............................................ 306 MOVSF .................................................................... 303 MOVSS .................................................................... 304 PUSHL ..................................................................... 304 SUBFSR .................................................................. 305 SUBULNK ................................................................ 305 Syntax ...................................................................... 301 External Clock Input ........................................................... 26 F Fail-Safe Clock Monitor ........................................... 239, 251 Interrupts in Power Managed Modes ....................... 252 POR or Wake from Sleep ........................................ 252 WDT During Oscillator Failure ................................. 251 Fast Register Stack ........................................................... 58 Flash Program Memory ..................................................... 77 Associated Registers ................................................. 79 Control Registers ....................................................... 78 Reading ..................................................................... 78 TABLAT (Table Latch) Register ................................ 78 Table Reads and Table Writes .................................. 77 TBLPTR (Table Pointer) Register .............................. 78 FSCM. See Fail-Safe Clock Monitor. G General Call Address Support ......................................... 176 GOTO .............................................................................. 280 H Hardware Multiplier ............................................................ 81 Introduction ................................................................ 81 Operation ................................................................... 81 Performance Comparison .......................................... 81 High/Low-Voltage Detect ................................................. 233 Applications ............................................................. 236 Associated Registers ............................................... 237 Characteristics ......................................................... 330 Current Consumption .............................................. 235 Effects of a Reset .................................................... 237 Operation ................................................................. 234 During Sleep .................................................... 237 Setup ....................................................................... 235 Start-up Time ........................................................... 235 Typical Application ................................................... 236 HLVD. See High/Low-Voltage Detect. ............................. 233 I I/O Ports ............................................................................ 97 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 186 Baud Rate Generator .............................................. 179 Bus Collision During a Repeated Start Condition .................. 190 During a Stop Condition .................................. 191 Clock Arbitration ...................................................... 180 Clock Stretching ...................................................... 172 10-Bit Slave Receive Mode (SEN = 1) ............ 172 10-Bit Slave Transmit Mode ............................ 172 7-Bit Slave Receive Mode (SEN = 1) .............. 172 7-Bit Slave Transmit Mode .............................. 172 Clock Synchronization and the CKP bit (SEN = 1) .. 173 Effects of a Reset .................................................... 187 General Call Address Support ................................. 176 I2C Clock Rate w/BRG ............................................ 179 Master Mode ............................................................ 177 Operation ......................................................... 178 Reception ........................................................ 183 Repeated Start Timing ..................................... 182 Start Condition Timing ..................................... 181 Transmission ................................................... 183 Multi-Master Communication, Bus Collision and Arbitration ........................................................ 187 Multi-Master Mode ................................................... 187 Operation ................................................................. 166 |
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