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PIC18F2610E/SOSQTP Datasheet(PDF) 370 Page - Microchip Technology |
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PIC18F2610E/SOSQTP Datasheet(HTML) 370 Page - Microchip Technology |
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370 / 376 page  PIC18F2X1X/4X1X DS39636D-page 372 © 2009 Microchip Technology Inc. T Table Pointer Operations (table) ........................................ 78 Table Reads/Table Writes .................................................. 58 TBLRD ............................................................................. 297 TBLWT ............................................................................. 298 Time-out in Various Situations (table) ................................ 47 Timer0 .............................................................................. 115 16-Bit Mode Timer Reads and Writes ...................... 116 Associated Registers ............................................... 117 Clock Source Edge Select (T0SE Bit) ...................... 116 Clock Source Select (T0CS Bit) ............................... 116 Operation ................................................................. 116 Overflow Interrupt .................................................... 117 Prescaler .................................................................. 117 Prescaler. See Prescaler, Timer0. Timer1 .............................................................................. 119 16-Bit Read/Write Mode ........................................... 121 Associated Registers ............................................... 123 Interrupt .................................................................... 122 Operation ................................................................. 120 Oscillator .......................................................... 119, 121 Oscillator Layout Considerations ............................. 122 Overflow Interrupt .................................................... 119 Resetting, Using the CCP Special Event Trigger ..... 122 Special Event Trigger (ECCP) ................................. 140 TMR1H Register ...................................................... 119 TMR1L Register ....................................................... 119 Use as a Real-Time Clock ....................................... 122 Timer2 .............................................................................. 125 Associated Registers ............................................... 126 Interrupt .................................................................... 126 Operation ................................................................. 125 Output ...................................................................... 126 PR2 Register .................................................... 136, 141 TMR2 to PR2 Match Interrupt .......................... 136, 141 Timer3 .............................................................................. 127 16-Bit Read/Write Mode ........................................... 129 Associated Registers ............................................... 129 Operation ................................................................. 128 Oscillator .......................................................... 127, 129 Overflow Interrupt ............................................ 127, 129 Special Event Trigger (CCP) .................................... 129 TMR3H Register ...................................................... 127 TMR3L Register ....................................................... 127 Timing Diagrams A/D Conversion ........................................................ 350 Acknowledge Sequence .......................................... 186 Asynchronous Reception ......................................... 205 Asynchronous Transmission .................................... 203 Asynchronous Transmission (Back to Back) ........... 203 Automatic Baud Rate Calculation ............................ 201 Auto-Wake-up Bit (WUE) During Normal Operation 206 Auto-Wake-up Bit (WUE) During Sleep ................... 206 Baud Rate Generator with Clock Arbitration ............ 180 BRG Overflow Sequence ......................................... 201 BRG Reset Due to SDA Arbitration During Start Condi- tion ................................................................... 189 Brown-out Reset (BOR) ........................................... 336 Bus Collision During a Repeated Start Condition (Case 1) ...................................................................... 190 Bus Collision During a Repeated Start Condition (Case 2) ...................................................................... 190 Bus Collision During a Start Condition (SCL = 0) .... 189 Bus Collision During a Start Condition (SDA only) .. 188 Bus Collision During a Stop Condition (Case 1) ...... 191 Bus Collision During a Stop Condition (Case 2) ...... 191 Bus Collision for Transmit and Acknowledge .......... 187 Capture/Compare/PWM (CCP) ............................... 338 CLKO and I/O .......................................................... 335 Clock Synchronization ............................................. 173 Clock/Instruction Cycle .............................................. 59 Example SPI Master Mode (CKE = 0) ..................... 340 Example SPI Master Mode (CKE = 1) ..................... 341 Example SPI Slave Mode (CKE = 0) ....................... 342 Example SPI Slave Mode (CKE = 1) ....................... 343 External Clock (All Modes except PLL) ................... 333 Fail-Safe Clock Monitor ........................................... 252 First Start Bit Timing ................................................ 181 Full-Bridge PWM Output .......................................... 145 Half-Bridge PWM Output ......................................... 144 High/Low-Voltage Detect Characteristics ................ 330 High-Voltage Detect (VDIRMAG = 1) ...................... 236 I2C Bus Data ............................................................ 344 I2C Bus Start/Stop Bits ............................................ 344 I2C Master Mode (7 or 10-Bit Transmission) ........... 184 I2C Master Mode (7-Bit Reception) .......................... 185 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 170 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 175 I2C Slave Mode (10-Bit Transmission) .................... 171 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 168 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 174 I2C Slave Mode (7-Bit Transmission) ...................... 169 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ...................................... 176 I2C Stop Condition Receive or Transmit Mode ........ 186 Low-Voltage Detect (VDIRMAG = 0) ....................... 235 Master SSP I2C Bus Data ........................................ 346 Master SSP I2C Bus Start/Stop Bits ........................ 346 Parallel Slave Port (PIC18F4410/4510/4515/4610) . 339 Parallel Slave Port (PSP) Read ............................... 113 Parallel Slave Port (PSP) Write ............................... 113 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 150 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 150 PWM Direction Change ........................................... 147 PWM Direction Change at Near 100% Duty Cycle .. 147 PWM Output ............................................................ 136 Repeat Start Condition ............................................ 182 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ..................... 336 Send Break Character Sequence ............................ 207 Slave Synchronization ............................................. 159 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................................................ 49 SPI Mode (Master Mode) ......................................... 158 SPI Mode (Slave Mode, CKE = 0) ........................... 160 SPI Mode (Slave Mode, CKE = 1) ........................... 160 Synchronous Reception (Master Mode, SREN) ...... 210 Synchronous Transmission ..................................... 208 Synchronous Transmission (Through TXEN) .......... 209 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ............................................................... 49 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ................................................. 48 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ................................................. 48 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ............................................ 48 Timer0 and Timer1 External Clock .......................... 337 |
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