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DSPIC33FJ12GP201TE/ML Datasheet(PDF) 164 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML Datasheet(HTML) 164 Page - Microchip Technology |
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164 / 242 page  dsPIC33FJ12GP201/202 DS70264B-page 162 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-1: ADC1 MODULE BLOCK DIAGRAM S/H + - Conversion Conversion Logic VREF+(1) AVSS AVDD ADC1 16-bit ADC Output 00000 00101 00111 01001 00001 00010 00011 00100 00110 01000 AN8(3) AN9(3) AN2 AN4 AN7(3) AN0 AN3 AN1 AN5 CH1(2) CH2(2) CH3(2) CH0 AN5 AN2 AN8(3) VREF- AN4 AN1 AN7(3) VREF- AN3 AN0 AN9(3) AN6(3) VREF- AN1 VREF- VREF-(1) Sample/Sequence Control Sample CH1,CH2, CH3,CH0 Input MUX Control Input Switches S/H + - S/H + - S/H + - AN6(3) Buffer Result Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: AN6 through AN9 are not applicable to dsPIC33FJ12GP201 devices. |
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