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DSPIC30F0010AT-20E/S Datasheet(PDF) 231 Page - Microchip Technology

Part # DSPIC30F0010AT-20E/S
Description  High-Performance, 16-Bit Digital Signal Controllers
PDF  236 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F0010AT-20E/S Datasheet(HTML) 231 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS70150C-page 229
dsPIC30F6010A/6015
SPI Master Mode (CKE = 1) .................................... 201
SPI Slave Mode (CKE = 0) ...................................... 202
SPI Slave Mode (CKE = 1) ...................................... 203
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 1 ................................. 154
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 2 ................................. 155
Time-out Sequence on Power-up (MCLR
Tied to VDD) ..................................................... 154
TimerQ (QEI Module) External Clock ...................... 194
Timer1, 2, 3, 4, 5 External Clock .............................. 192
10-bit High-Speed A/D Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 212
10-bit High-Speed A/D Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ............................................... 213
Timing Requirements
Input Capture ........................................................... 195
Timing Specifications
Band Gap Start-up Time Requirements ................... 191
CAN I/O Requirements ............................................ 209
CLKOUT and I/O Characteristics ............................. 189
CLKOUT and I/O Requirements .............................. 189
External Clock Requirements .................................. 185
Internal Clock Examples .......................................... 187
I2C Bus Data Requirements (Master Mode) ............ 206
I2C Bus Data Requirements (Slave Mode) .............. 208
Motor Control PWM Requirements .......................... 197
Output Compare Requirements ............................... 195
PLL Clock ................................................................. 186
PLL Jitter .................................................................. 186
QEI External Clock Requirements ........................... 194
QEI Index Pulse Requirements ................................ 199
Quadrature Decoder Requirements ......................... 198
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 191
Simple OC/PWM Mode Requirements .................... 196
SPI Master Mode (CKE = 0) Requirements ............. 200
SPI Master Mode (CKE = 1) Requirements ............. 201
SPI Slave Mode (CKE = 0) Requirements ............... 202
SPI Slave Mode (CKE = 1) Requirements ............... 203
Timer1 External Clock Requirements ...................... 192
Timer2 and Timer4 External Clock Requirements ... 193
Timer3 and Timer5 External Clock Requirements ... 193
10-bit High-Speed A/D ............................................. 210
10-bit High-Speed A/D Conversion Requirements .. 214
Traps .................................................................................. 41
Hard and Soft ............................................................. 42
Sources ...................................................................... 41
Vectors ....................................................................... 42
U
UART
Address Detect Mode .............................................. 119
Auto-Baud Support .................................................. 120
Baud Rate Generator (BRG) .................................... 119
Disabling .................................................................. 117
Enabling and Setup .................................................. 117
Loopback Mode ....................................................... 119
Module Overview ..................................................... 115
Operation During CPU Sleep and Idle Modes ......... 120
Receiving Data ......................................................... 118
In 8-bit or 9-bit Data Mode ............................... 118
Interrupt ........................................................... 118
Receive Buffer (UxRXB) .................................. 118
Reception Error Handling ........................................ 118
Framing Error (FERR) ..................................... 119
Idle Status ....................................................... 119
Parity Error (PERR) ......................................... 119
Receive Break ................................................. 119
Receive Buffer Overrun Error (OERR Bit) ....... 118
Setting Up Data, Parity and Stop Bit Selections ...... 117
Transmitting Data .................................................... 117
In 8-bit Data Mode ........................................... 117
In 9-bit Data Mode ........................................... 117
Interrupt ........................................................... 118
Transmit Break ................................................ 118
Transmit Buffer (UxTXB) ................................. 117
UART1 Register Map .............................................. 121
UART2 Register Map .............................................. 121
Unit ID Locations ............................................................. 147
Universal Asynchronous Receiver Transmitter
Module (UART) ........................................................ 115
W
Wake-up from Sleep ........................................................ 147
Wake-up from Sleep and Idle ............................................ 43
Watchdog Timer (WDT) ........................................... 147, 158
Enabling and Disabling ............................................ 158
Operation ................................................................. 158
WWW Address ................................................................ 231
WWW, On-Line Support ...................................................... 5
Z
16-bit Up/Down Position Counter Mode ............................ 88
Count Direction Status ............................................... 88
Error Checking ........................................................... 88



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