DSPIC30F0010AT-20ESLASHS datasheet(161/236 Pages) MICROCHIP

161 / 236 page

DS70150C-page 159

dsPIC30F6010A/6015

If Watchdog Timer is enabled, then the processor will

wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO Status bits are both set.

21.5.2

IDLE MODE

In Idle mode, the clock to the CPU is shutdown while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

Several peripherals have a control bit in each module,

that allows them to operate during Idle.

LPRC fail-safe clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

• on any interrupt that is individually enabled (IE bit

is ‘1’) and meets the required priority level

• on any Reset (POR, BOR, MCLR)

• on WDT time-out

Upon wake-up from Idle mode, the clock is re-applied

to the CPU and instruction execution begins immedi-

ately, starting with the instruction following the PWRSAV

instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-up the processor. The processor will process the

interrupt and branch to the ISR. The Idle Status bit in

RCON register is set upon wake-up.

Any Reset, other than POR, will set the Idle Status bit.

On a POR, the Idle bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO Status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

21.6

Device Configuration Registers

The Configuration bits in each device Configuration

programmed by a device programmer, or by using the

In-Circuit Serial Programming™ (ICSP™) feature of the

device. Each device Configuration register is a 24-bit

used to hold configuration data. There are six device

Configuration registers available to the user:

FOSC (0xF80000): Oscillator Configuration

FWDT (0xF80002): Watchdog Timer

Configuration register

FBORPOR (0xF80004): BOR and POR

Configuration register

FBS (0xF80006): Boot Code Segment

Configuration register

FSS (0xF80008): Secure Code Segment

Configuration register

FGS (0xF8000A): General Code Segment

Configuration register

The placement of the Configuration bits is automatically

handled when you select the device in your device pro-

grammer. The desired state of the Configuration bits may

be specified in the source code (dependent on the lan-

guage tool used), or through the programming interface.

After the device has been programmed, the application

software may read the Configuration bit values through

the table read instructions. For additional information,

please refer to the “dsPIC30F/33F Programmers Refer-

ence Manual” (DS70157) and the “dsPIC30F Family

Reference Manual” (DS70046).

Note 1: If the code protection Configuration Fuse

bits (FBS(BSS<2:0>), FSS(SSS<2:0>),

FGS<GCP> and FGS<GWRP>) have

been programmed, an erase of the entire

code-protected device is only possible at

voltages VDD

≥ 4.5V.

2: This device supports an Advanced imple-

mentation

CodeGuard™

Security.

Please refer to the “CodeGuard Security”

chapter (DS70180) for information on

how CodeGuard Security may be used in

your application.

DSPIC30F0010AT-20E/S Datasheet(PDF) 161 Page - Microchip Technology

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