PIC16F1508TESSQTO datasheet(290/384 Pages) MICROCHIP

290 / 384 page

PIC16(L)F1508/9

DS41609A-page 290

Preliminary

 2011 Microchip Technology Inc.

25.2

FIXED DUTY CYCLE (FDC) MODE

In Fixed Duty Cycle (FDC) mode, every time the

accumulator overflows, the output is toggled. This

provides a 50% duty cycle, provided that the increment

value remains constant. For more information, see

Figure 25-2.

The FDC mode is selected by clearing the NxPFM bit

in the NCOxCON register.

25.3

PULSE FREQUENCY (PF) MODE

In Pulse Frequency (PF) mode, every time the accumu-

lator overflows, the output becomes active for one or

more clock periods. Once the clock period expires, the

output returns to an inactive state. This provides a

pulsed output.

The output becomes active on the rising clock edge

immediately following the overflow event. For more

information, see Figure 25-2.

The value of the active and inactive states depends on

the polarity bit, NxPOL in the NCOxCON register.

The PF mode is selected by setting the NxPFM bit in

the NCOxCON register.

25.3.1

OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the out-

put can vary in width by multiple clock periods. Various

pulse widths are selected with the NxPWS<2:0> bits in

the NCOxCLK register.

When the selected pulse width is greater than the

accumulator overflow time frame, the output of the

NCOx operation is indeterminate.

25.4

OUTPUT POLARITY CONTROL

The last stage in the NCOx module is the output polar-

ity. The NxPOL bit in the NCOxCON register selects the

output polarity. Changing the polarity while the inter-

rupts are enabled will cause an interrupt for the result-

ing output transition.

The NCOx output can be used internally by source

code or other peripherals. Accomplish this by reading

the NxOUT (read-only) bit of the NCOxCON register.

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