PIC24HJ128GP310 datasheet(277/286 Pages) MICROCHIP

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DS70175F-page 275

PIC24HJXXXGPX06/X08/X10

APPENDIX A: REVISION HISTORY

Revision A (February 2006)

• Initial release of this document

Revision B (March 2006)

• Updated the Configuration Bits Description table

(Table 20.1)

• Updated registers and register maps

• Updated Section 15.0 “Serial Peripheral Interface

(SPI)”

• Updated Section 23.0 “Electrical Characteristics”

• Updated pinout diagrams

• Additional minor corrections throughout document

text

Revision C (May 2006)

• Updated Section 23.0 “Electrical Characteristics”

• Updated the Configuration Bits Description table

(Table 20.1)

• Additional minor corrections throughout document

text

Revision D (July 2006)

• Added FBS and FSS Device Configuration regis-

ters (see Table 20-1) and corresponding bit field

descriptions (see Table 20-2). These added regis-

ters replaced the former RESERVED1 and

RESERVED2 registers.

• Added INTTREG Interrupt Control and Status

and Status Registers”. See also Register 6-33.)

• Added Core Registers BSRAM and SSRAM (see

Section 3.2.7 “Data Ram Protection Feature”)

• Clarified Fail-Safe Clock Monitor operation (see

Section 8.3 “Fail-Safe Clock Monitor (FSCM)”)

• Updated COSC<2:0> and NOSC<2:0> bit config-

urations in OSCCON register (see Register 8-1)

• Updated CLKDIV register bit configurations (see

• Added Word Write Cycle Time parameter (TWW)

to Program Flash Memory (see Table 23-12)

• Noted exceptions to Absolute Maximum Ratings

on I/O pin output current (see Section 23.0

“Electrical Characteristics”)

• Added ADC2 Event Trigger for Timer4/5

(Section 12.0 “Timer2/3, Timer4/5, Timer6/7

and Timer8/9”)

• Corrected mislabeled I2COV bit in I2CxSTAT

• Removed AD26a, AD27a, AD28a, AD26b, AD27b

and AD28b from Table 23-34 (A/D Module)

• Revised Table 23-36 (AD63)

Revision E (June 2007)

• Updated Section 23.0 “Electrical Characteristics”

• Additional minor corrections throughout document

text

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