PIC24FJ128GA310 datasheet(297/406 Pages) MICROCHIP

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 2010-2011 Microchip Technology Inc.

DS39996F-page 297

PIC24FJ128GA310 FAMILY

24.2

Extended DMA Operations

In addition to the standard features available on all

12-bit A/D Converters, PIC24FJ128GA310 family

devices implement a limited extension of DMA func-

tionality. This extension adds features that work with

the device’s DMA Controller to expand the A/D

module’s data storage abilities beyond the module’s

built-in buffer.

The Extended DMA functionality is controlled by the

DMAEN bit (AD1CON1<10>); setting this bit enables

the functionality. The DMABM bit (AD1CON1<11>)

configures how the DMA feature operates.

24.2.1

EXTENDED BUFFER MODE

Extended Buffer mode (DMABM = 1) is useful for stor-

ing the results of conversions on the upper channels

(i.e., 26 and above), which do not have their own

memory mapped buffers inside the A/D module. It can

also be used to store the conversion results on any A/D

channel in any implemented address in data RAM.

In Extended Buffer mode, all data from the A/D Buffer

RAM. Conversion data is written to a destination

specified by the DMA Controller, specifically by the

DMADST register. This allows users to read the con-

version results of channels above 26, which do not

have their own memory mapped A/D buffer locations,

from data memory.

When using Extended Buffer mode, always set the

BUFREGEN bit to disable FIFO operation. In addition,

disable the Split Buffer mode by clearing the BUFM bit.

24.2.2

PIA MODE

When DMABM = 0, the A/D module is configured to

function with the DMA controller for Peripheral Indirect

Addressing (PIA) mode operations. In this mode, the

A/D module generates an 11-bit Indirect Address (IA).

This is ORed with the destination address in the DMA

Controller to define where the A/D conversion data will

be stored.

In PIA mode, the buffer space is created as a series of

contiguous smaller buffers, one per analog channel. The

size of the channel buffer determines how many analog

channels can be accommodated. The size of the buffer

is selected by the DMABL bits (AD1CON4<2:0>). The

size options range from a single word per buffer to

128 words. Each channel is allocated a buffer of this

size, regardless of whether or not the channel will

actually have conversion data.

The IA is created by combining the base address within

a channel buffer with three to five bits (depending on

the buffer size) to identify the channel. The base

address ranges from zero to seven bits wide, depend-

ing on the buffer size. The address is right-padded with

a ‘0’ in order to maintain address alignment in the data

space. The concatenated channel and base address

bits are then left-padded with zeroes, as necessary, to

complete the 11-bit IA.

The IA is configured to auto-increment during write

operations by using the SMPI bits (AD1CON2<6:2>).

As with PIA operations for any DMA-enabled module,

the base destination address in the DMADST register

must be masked properly to accommodate the IA.

Table 24-1 shows how complete addresses are

formed. Note that the address masking varies for each

buffer size option. Because of masking requirements,

some address ranges may not be available for certain

buffer sizes. Users should verify that the DMA base

address is compatible with the buffer size selected.

Figure 24-2 shows how the parts of the address define

the buffer locations in data memory. In this case, the

module “allocates” 256 bytes of data RAM (1000h to

1100h) for 32 buffers of four words each. However, this

is not a hard allocation and nothing prevents these

locations from being used for other purposes. For

example, in the current case, if Analog Channels 1, 3

and 8 are being sampled and converted, conversion

data will only be written to the channel buffers, starting

at 1008h, 1018h and 1040h. The holes in PIA buffer

space can be used for any other purpose. It is the

user’s responsibility to keep track of buffer locations

and preventing data overwrites.

24.3

A/D Operation with VBAT

One of the A/D channels is connected to the VBAT pin

to monitor the VBAT voltage. This allows monitoring the

VBAT pin voltage (battery voltage) with no external con-

nection. The voltage measured, using the A/D VBAT

monitor, is VBAT/2. The voltage can be calculated by

reading A/D = ((VBAT/2)/VDD) * 1024 for 10-bit A/D and

((VBAT/2)/VDD) * 4096 for 12 bit A/D.

When using the VBAT A/D monitor:

• Connect the A/D channel to ground to discharge

the sample capacitor.

• Because of the high-impedance of VBAT, select

higher sampling time to get an accurate reading.

Since the VBAT pin is connected to the A/D during

sampling, to prolong the VBAT battery life, the

recommendation is to select the VBAT channel when

needed.

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