PIC24FJ128GA310 datasheet(315/406 Pages) MICROCHIP

315 / 406 page

 2010-2011 Microchip Technology Inc.

DS39996F-page 315

PIC24FJ128GA310 FAMILY

25.0

TRIPLE COMPARATOR

MODULE

The triple comparator module provides three dual input

comparators. The inputs to the comparator can be

configured to use any one of five external analog inputs

(CxINA, CxINB, CxINC, CxIND and VREF+) and a

voltage reference input from one of the internal band

gap references or the comparator voltage reference

generator (VBG, VBG/2, VBG/6 and CVREF).

The comparator outputs may be directly connected to

the CxOUT pins. When the respective COE equals ‘1’,

the I/O pad logic makes the unsynchronized output of

the comparator available on the pin.

A simplified block diagram of the module in shown in

Figure 25-1. Diagrams of the possible individual

comparator configurations are shown in Figure 25-2.

Each comparator has its own control register,

CMxCON (Register 25-1), for enabling and configuring

its operation. The output and event status of all three

comparators is provided in the CMSTAT register

(Register 25-2).

FIGURE 25-1:

TRIPLE COMPARATOR MODULE BLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual

”,

Section

46.

“Scalable

Comparator

Module”

(DS39734). The information in

this data sheet supersedes the information

in the FRM.

VIN-

VIN+

CXINB

CXINC

CXINA

CXIND

CVREF

VBG

VIN-

VIN+

VIN-

VIN+

COE

C1OUT

CPOL

Trigger/Interrupt

Logic

CEVT

EVPOL<1:0>

COUT

Input

Select

Logic

CCH<1:0>

CREF

COE

C2OUT

CPOL

Trigger/Interrupt

Logic

CEVT

EVPOL<1:0>

COUT

COE

C3OUT

CPOL

Trigger/Interrupt

Logic

CEVT

EVPOL<1:0>

COUT

VBG/2

VBG/6

VREF+

CVREFM<1:0>(1)

VREF+

CVREFP(1)

Note 1:

Refer to the CVRCON register (Register 26-1) for bit details.

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