PIC24FJ128GA310 datasheet(324/406 Pages) MICROCHIP

324 / 406 page

PIC24FJ128GA310 FAMILY

DS39996F-page 324

 2010-2011 Microchip Technology Inc.

FIGURE 27-1:

TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR

CAPACITANCE MEASUREMENT

27.2

Measuring Time

Time measurements on the pulse width can be similarly

performed using the A/D module’s internal capacitor

(CAD) and a precision resistor for current calibration.

Figure 27-2 displays the external connections used for

time measurements, and how the CTMU and A/D

modules are related in this application. This example

also shows both edge events coming from the external

CTEDG pins, but other configurations using internal

edge sources are possible.

27.3

Pulse Generation and Delay

The CTMU module can also generate an output pulse

with edges that are not synchronous with the device’s

system clock. More specifically, it can generate a pulse

with a programmable delay from an edge event input to

the module.

When the module is configured for pulse generation

delay by setting the TGEN bit (CTMUCON1<12>), the

internal current source is connected to the B input of

Comparator 2. A capacitor (CDELAY) is connected to

the Comparator 2 pin, C2INB, and the comparator

voltage reference, CVREF, is connected to C2INA.

CVREF is then configured for a specific trip point. The

module begins to charge CDELAY when an edge event

is detected. When CDELAY charges above the CVREF

trip point, a pulse is output on CTPLS. The length of the

pulse delay is determined by the value of CDELAY and

the CVREF trip point.

Figure 27-3 illustrates the external connections for

pulse generation, as well as the relationship of the

different analog modules required. While CTED1 is

shown as the input pulse source, other options are

available. A detailed discussion on pulse generation

with the CTMU module is provided in the “PIC24F

Family Reference Manual”

PIC24F Device

A/D Converter

CTMU

ANx

CAPP

Output Pulse

EDG1

EDG2

RPR

ANY

Timer1

Current Source

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