PIC24FJ128GA310 datasheet(396/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 396

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Data Memory

Address Space............................................................ 43

Extended Data Space (EDS) ...................................... 65

Memory Map ............................................................... 43

Near Data Space ........................................................ 44

SFR Space.................................................................. 44

Software Stack............................................................ 68

Space Organization, Alignment .................................. 44

Data Signal Modulator....................................................... 249

Data Signal Modulator (DSM) ........................................... 249

DC Characteristics

Comparator ............................................................... 368

Comparator Voltage Reference ................................ 368

CTMU Current Source .............................................. 367

I/O Pin Input Specifications ....................................... 365

I/O Pin Output Specifications .................................... 366

Idle Current ............................................................... 362

Operating Current ..................................................... 361

Power-Down Current ................................................ 363

Program Memory ...................................................... 366

Resets....................................................................... 364

Temperature and Voltage Specifications .................. 361

Vbat Operating Voltage Specifications ..................... 367

Development Support ....................................................... 347

Device Features

100-Pin........................................................................ 15

64-Pin.......................................................................... 13

80-Pin.......................................................................... 14

Direct Memory Access Controller. See DMA.

DMA .................................................................................... 75

Channel Trigger Sources ............................................ 82

Peripheral Module Disable (PMD) .............................. 78

Summary of Operations .............................................. 76

Types of Transfers ...................................................... 77

Typical Setup .............................................................. 78

DMA Controller.................................................................... 12

Electrical Characteristics

Absolute Maximum Ratings ...................................... 359

Capacitive Loading on Output Pin ............................ 369

CLKO and I/O Timing................................................ 372

External Clock Timing ............................................... 370

High/Low-Voltage Detect .......................................... 368

Internal Voltage Regulator Specifications ................. 367

PLL Clock Timing Specifications............................... 371

RC Oscillator Start-up Time ...................................... 371

Reset and Brown-out Reset Requirements .............. 373

Thermal Conditions ................................................... 360

V/F Graph ................................................................. 360

Enhanced Parallel Master Port (EPMP)............................ 253

Enhanced Parallel Master Port. See EPMP...................... 253

EPMP

Key Features............................................................. 253

Package Variations ................................................... 253

Equations

16-Bit, 32-Bit CRC Polynomials................................ 290

A/D Conversion Clock Period ................................... 311

Baud Rate Reload Calculation.................................. 235

Calculating the PWM Period..................................... 214

Calculation for Maximum PWM Resolution .............. 215

Relationship Between Device and

SPI Clock Speed .............................................. 231

UART Baud Rate with BRGH = 0 ............................. 242

UART Baud Rate with BRGH = 1 ............................. 242

Errata .................................................................................. 10

Extended Data Space (EDS) ............................................ 253

Flash Configuration Word Locations................................. 333

Flash Configuration Words ................................................. 42

Flash Program Memory ...................................................... 83

and Table Instructions ................................................ 83

Enhanced ICSP Operation ......................................... 84

JTAG Operation.......................................................... 84

Programming Algorithm .............................................. 86

Programming Operations............................................ 84

RTSP Operation ......................................................... 84

Single-Word Programming ......................................... 88

High/Low-Voltage Detect (HLVD) ..................................... 331

I/O Ports

Analog Port Pins Configuration (ANSx) .................... 168

Analog/Digital Function of an I/O Pin........................ 168

Input Change Notification ......................................... 172

Open-Drain Configuration......................................... 168

Parallel (PIO) ............................................................ 167

Peripheral Pin Select ................................................ 173

Pull-ups and Pull-Downs........................................... 172

Selectable Input Sources.......................................... 174

I2C

Clock Rates .............................................................. 235

Communicating as Master in Single

Master Environment ......................................... 233

Reserved Addresses ................................................ 235

Setting Baud Rate as Bus Master............................. 235

Slave Address Masking ............................................ 235

Input Capture

32-Bit Cascaded Mode ............................................. 206

Operations ................................................................ 206

Synchronous and Trigger Modes.............................. 205

Input Capture with Dedicated Timers ............................... 205

Input Voltage Levels for Port or Pin Tolerated

Description Input....................................................... 168

Instruction Set

Overview................................................................... 353

Summary .................................................................. 351

Symbols Used in Opcode Descriptions .................... 352

Interfacing Program and Data Spaces................................ 69

Inter-Integrated Circuit. See I2C. ...................................... 233

Internet Address ............................................................... 400

Interrupt Vector Table (IVT) ................................................ 95

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