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PIC24FJ128GA310 Datasheet(PDF) 117 Page - Microchip Technology |
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PIC24FJ128GA310 Datasheet(HTML) 117 Page - Microchip Technology |
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117 / 406 page ![]() 2010-2011 Microchip Technology Inc. DS39996F-page 117 PIC24FJ128GA310 FAMILY bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — RTCIE DMA5IE — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 —INT4IE(1) INT3IE(1) — —MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 DMA5IE: DMA Channel 5 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information. |
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