PIC24FJ128GA310 datasheet(167/406 Pages) MICROCHIP

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DS39996F-page 167

PIC24FJ128GA310 FAMILY

11.0

I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSCI/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger (ST) inputs for improved noise immunity.

11.1

Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

All port pins have three registers directly associated

with their operation as digital I/O and one register asso-

ciated with their operation as analog input. The Data

Direction register (TRISx) determines whether the pin

is an input or an output. If the data direction bit is a ‘1’,

then the pin is an input. All port pins are defined as

inputs after a Reset. Reads from the Output Latch reg-

ister (LATx), read the latch; writes to the latch, write the

latch. Reads from the port (PORTx), read the port pins;

writes to the port pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers, and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is regarded as a

dedicated port because there is no other competing

source of inputs. RC13 and RC14 can be input ports

only; they cannot be configured as outputs.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section 12. “I/O Ports with Peripheral

Pin Select (PPS)”

(DS39711). The infor-

mation in this data sheet supersedes the

information in the FRM.

WR LAT +

TRIS Latch

I/O Pin

WR PORT

Data Bus

Data Latch

Read PORT

Read TRIS

WR TRIS

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LAT

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