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PIC24FJ128GA310 Datasheet(PDF) 200 Page - Microchip Technology |
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PIC24FJ128GA310 Datasheet(HTML) 200 Page - Microchip Technology |
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200 / 406 page  PIC24FJ128GA310 FAMILY DS39996F-page 200 2010-2011 Microchip Technology Inc. FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TMR3 TMR2 Set T3IF (T5IF) Equal Comparator PR3 PR2 Reset LSB MSB Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral Pin Select (PPS)” for more information. 3: The A/D event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. Data Bus<15:0> TMR3HLD Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 16 16 Q QD CK TGATE 0 1 TON TCKPS<1:0> Prescaler 1, 8, 64, 256 2 TCY TCS(2) TGATE(2) Gate T2CK Sync A/D Event Trigger(3) Sync (T4CK) (PR5) (PR4) (TMR5HLD) (TMR5) (TMR4) 1x 01 00 |
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