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DSPIC33FJ64GP706 Datasheet(PDF) 228 Page - Microchip Technology |
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DSPIC33FJ64GP706 Datasheet(HTML) 228 Page - Microchip Technology |
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228 / 322 page  dsPIC33FJXXXGPX06/X08/X10 DS70286C-page 226 © 2009 Microchip Technology Inc. FIGURE 21-1: ADCx MODULE BLOCK DIAGRAM SAR ADC S/H0 S/H1 ADC1BUF0 AN0 ANy(3) AN1 VREF- CH0SB<4:0> CH0NA CH0NB + - AN0 AN3 CH123SA AN9 VREF- CH123SB CH123NA CH123NB AN6 + - S/H2 AN1 AN4 CH123SA AN10 VREF- CH123SB CH123NA CH123NB AN7 + - S/H3 AN2 AN5 CH123SA AN11 VREF- CH123SB CH123NA CH123NB AN8 + - CH1(2) CH0 CH2(2) CH3(2) CH0SA<4:0> CHANNEL SCAN CSCNA Alternate VREF+(1) AVDD AVSS VREF-(1) Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: For 64-pin devices, y = 17; for 80-pin devices, y = 23; for 100-pin devices, y = 31; for ADC2, y = 15. Input Selection VREFH VREFL |
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