DSPIC33FJ64GP706 datasheet(161/322 Pages) MICROCHIP

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DS70286C-page 159

dsPIC33FJXXXGPX06/X08/X10

13.0 TIMER2/3, TIMER4/5, TIMER6/7

AND TIMER8/9

The Timer2/3, Timer4/5, Timer6/7 and Timer8/9

modules are 32-bit timers, which can also be

configured as four independent 16-bit timers with

selectable operating modes.

As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and

Timer8/9 operate in three modes:

• Two Independent 16-bit Timers (e.g., Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit Timer

• Single 32-bit Synchronous Counter

They also support these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

• Time Base for Input Capture and Output Compare

Modules (Timer2 and Timer3 only)

• ADC1 Event Trigger (Timer2/3 only)

• ADC2 Event Trigger (Timer4/5 only)

Individually, all eight of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the event trigger; this

is implemented only with Timer2/3. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON, T3CON, T4CON,

T5CON, T6CON, T7CON, T8CON and T9CON

registers. T2CON, T4CON, T6CON and T8CON are

shown in generic form in Register 13-1. T3CON,

T5CON,

T7CON

and

T9CON

are

shown

For 32-bit timer/counter operation, Timer2, Timer4,

Timer6 or Timer8 is the least significant word; Timer3,

Timer5, Timer7 or Timer9 is the most significant word

of the 32-bit timers.

To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9

for 32-bit operation:

Set the corresponding T32 control bit.

Select the prescaler ratio for Timer2, Timer4,

Timer6 or Timer8 using the TCKPS<1:0> bits.

Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

Load the timer period value. PR3, PR5, PR7 or

PR9 contains the most significant word of the

value, while PR2, PR4, PR6 or PR8 contains the

least significant word.

If interrupts are required, set the interrupt enable

bit, T3IE, T5IE, T7IE or T9IE. Use the priority

bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or

T9IP<2:0>, to set the interrupt priority. While

Timer2, Timer4, Timer6 or Timer8 control the

timer, the interrupt appears as a Timer3, Timer5,

Timer7 or Timer9 interrupt.

Set the corresponding TON bit.

The timer value at any point is stored in the register

pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or

TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always

contains the most significant word of the count, while

TMR2, TMR4, TMR6 or TMR8 contains the least

significant word.

To configure any of the timers for individual 16-bit

operation:

Clear the T32 bit corresponding to that timer.

Select the timer prescaler ratio using the

TCKPS<1:0> bits.

Set the Clock and Gating modes using the TCS

and TGATE bits.

Load the timer period value into the PRx

If interrupts are required, set the interrupt enable

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

Set the TON bit.

A block diagram for a 32-bit timer pair (Timer4/5)

example is shown in Figure 13-1 and a timer (Timer4)

operating in 16-bit mode example is shown in

Figure 13-2.

Note:

This data sheet summarizes the features

of the dsPIC33FJXXXGPX06/X08/X10

family of devices. However, it is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to Section 11.

“Timers” (DS70205) in the “dsPIC33F

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

Note:

For 32-bit operation, T3CON, T5CON,

T7CON and T9CON control bits are

ignored. Only T2CON, T4CON, T6CON

and T8CON control bits are used for setup

and control. Timer2, Timer4, Timer6 and

Timer8 clock and gate inputs are utilized

for the 32-bit timer modules, but an

interrupt is generated with the Timer3,

Timer5, Ttimer7 and Timer9 interrupt

flags.

Note:

Only Timer2 and Timer3 can trigger a

DMA data transfer.

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