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PIC16F882-I Datasheet(PDF) 319 Page - Microchip Technology |
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PIC16F882-I Datasheet(HTML) 319 Page - Microchip Technology |
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319 / 328 page  © 2009 Microchip Technology Inc. DS41291F-page 317 PIC16F882/883/884/886/887 EUSART ........................................................................... 151 Associated Registers Baud Rate Generator........................................ 163 Asynchronous Mode ................................................. 153 12-bit Break Transmit and Receive .................. 169 Associated Registers Receive ..................................................... 159 Transmit.................................................... 155 Auto-Wake-up on Break ................................... 168 Baud Rate Generator (BRG) ............................ 163 Clock Accuracy ................................................. 160 Receiver............................................................ 156 Setting up 9-bit Mode with Address Detect....... 158 Transmitter........................................................ 153 Baud Rate Generator (BRG) Auto Baud Rate Detect ..................................... 167 Baud Rate Error, Calculating ............................ 163 Baud Rates, Asynchronous Modes .................. 164 Formulas ........................................................... 163 High Baud Rate Select (BRGH Bit) .................. 163 Synchronous Master Mode ............................... 171, 175 Associated Registers Receive ..................................................... 174 Transmit.................................................... 172 Reception.......................................................... 173 Requirements, Synchronous Receive .............. 266 Requirements, Synchronous Transmission ...... 266 Timing Diagram, Synchronous Receive ........... 266 Timing Diagram, Synchronous Transmission ... 266 Transmission .................................................... 171 Synchronous Slave Mode Associated Registers Receive ..................................................... 176 Transmit.................................................... 175 Reception.......................................................... 176 Transmission .................................................... 175 F Fail-Safe Clock Monitor....................................................... 71 Fail-Safe Condition Clearing ....................................... 71 Fail-Safe Detection ..................................................... 71 Fail-Safe Operation ..................................................... 71 Reset or Wake-up from Sleep..................................... 71 Firmware Instructions........................................................ 231 Flash Program Memory .................................................... 111 Writing....................................................................... 117 Fuses. See Configuration Bits G General Call Address Support .......................................... 192 General Purpose Register File............................................ 22 I I2C (MSSP Module) ACK Pulse......................................................... 189, 190 Addressing ................................................................ 190 Read/Write Bit Information (R/W Bit) ........................ 190 Reception.................................................................. 190 Serial Clock (RC3/SCK/SCL).................................... 190 Slave Mode ............................................................... 189 Transmission............................................................. 190 I2C Master Mode Reception.............................................. 198 I2C Master Mode Repeated Start Condition Timing.......... 197 I2C Module Acknowledge Sequence Timing................................ 201 Baud Rate Generator................................................ 195 BRG Block Diagram ................................................. 195 BRG Reset Due to SDA Arbitration During Start Condition.................................................. 205 BRG Timing .............................................................. 195 Bus Collision Acknowledge .................................................... 203 Repeated Start Condition ................................. 206 Repeated Start Condition Timing (Case1)........ 206 Repeated Start Condition Timing (Case2)........ 206 Start Condition.................................................. 204 Start Condition Timing .............................. 204, 205 Stop Condition .................................................. 207 Stop Condition Timing (Case 1) ....................... 207 Stop Condition Timing (Case 2) ....................... 207 Bus Collision timing .................................................. 203 Clock Arbitration ....................................................... 202 Clock Arbitration Timing (Master Transmit) .............. 202 Effect of a Reset ....................................................... 202 General Call Address Support .................................. 192 Master Mode............................................................. 193 Master Mode 7-bit Reception Timing........................ 200 Master Mode Operation ............................................ 194 Master Mode Start Condition Timing ........................ 196 Master Mode Support ............................................... 193 Master Mode Transmission ...................................... 198 Master Mode Transmit Sequence ............................ 194 Multi-Master Mode .................................................... 203 Repeat Start Condition Timing Waveform ................ 197 Sleep Operation........................................................ 202 Stop Condition Receive or Transmit Timing ............. 202 Stop Condition Timing .............................................. 201 Waveforms for 7-bit Reception ................................. 191 Waveforms for 7-bit Transmission ............................ 191 ID Locations...................................................................... 227 In-Circuit Debugger........................................................... 229 In-Circuit Serial Programming (ICSP)............................... 227 Indirect Addressing, INDF and FSR registers..................... 37 Instruction Format............................................................. 231 Instruction Set................................................................... 231 ADDLW..................................................................... 233 ADDWF .................................................................... 233 ANDLW..................................................................... 233 ANDWF .................................................................... 233 BCF .......................................................................... 233 BSF........................................................................... 233 BTFSC ...................................................................... 233 BTFSS ...................................................................... 234 CALL......................................................................... 234 CLRF ........................................................................ 234 CLRW ....................................................................... 234 CLRWDT .................................................................. 234 COMF ....................................................................... 234 DECF........................................................................ 234 DECFSZ ................................................................... 235 GOTO ....................................................................... 235 INCF ......................................................................... 235 INCFSZ..................................................................... 235 IORLW ...................................................................... 235 IORWF...................................................................... 235 MOVF ....................................................................... 236 MOVLW .................................................................... 236 MOVWF.................................................................... 236 NOP.......................................................................... 236 RETFIE..................................................................... 237 RETLW ..................................................................... 237 |
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