PIC16F882-I datasheet(187/328 Pages) MICROCHIP

187 / 328 page

DS41291F-page 185

PIC16F882/883/884/886/887

13.3.3

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave is to broadcast data by the software

protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

a normal received byte (interrupts and Status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. This, then,

would give waveforms for SPI communication as

shown in Figure 13-2, Figure 13-4 and Figure 13-5,

where the MSb is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one

of the following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 13-2 shows the waveforms for Master mode.

When the CKE bit of the SSPSTAT register is set, the

SDO data is valid before there is a clock edge on SCK.

The change of the input sample is shown based on the

state of the SMP bit of the SSPSTAT register. The time

when the SSPBUF is loaded with the received data is

shown.

FIGURE 13-2:

SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7

bit 0

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit7

bit 0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q2

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