AT80SND2CMP3B datasheet(128/242 Pages) ATMEL

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4341H–MP3–10/07

AT8xC51SND2C/MP3B

Table 16-11. UEPINT Register

UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register

Reset Value = 0000 0000b

Table 16-12. UEPDATX Register

UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)

Reset Value = XXh

EP2INT

EP1INT

EP0INT

Bit Number

Bit

Mnemonic

Description

7 - 3

Reserved

The value read from these bits is always 0. Do not set these bits.

EP2INT

Endpoint 2 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared.

EP1INT

Endpoint 1 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared.

EP0INT

Endpoint 0 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared.

FDAT7

FDAT6

FDAT5

FDAT4

FDAT3

FDAT2

FDAT1

FDAT0

Bit Number

Bit

Mnemonic

Description

7 - 0

FDAT7:0

Endpoint X FIFO Data

Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the Endpoint X

(see EPNUM).

AT80SND2CMP3B Datasheet(PDF) 128 Page - ATMEL Corporation

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