AT80SND2CMP3B datasheet(178/242 Pages) ATMEL

178 / 242 page

178

4341H–MP3–10/07

AT8xC51SND2C/MP3B

20.8

Registers

Table 20-3.

SCON Register

SCON (S:98h) – Serial Control Register

Reset Value = 0000 0000b

FE/SM0

OVR/SM1

SM2

REN

TB8

RB8

Bit Number

Bit

Mnemonic

Description

Framing Error Bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be cleared by software.

SM0

Serial Port Mode Bit 0

Refer to Table 20-1 for mode selection.

SM1

Serial Port Mode Bit 1

Refer to Table 20-1 for mode selection.

SM2

Serial Port Mode Bit 2

Set to enable the multiprocessor communication and automatic address recognition

features.

Clear to disable the multiprocessor communication and automatic address recognition

features.

REN

Receiver Enable Bit

Set to enable reception.

Clear to disable reception.

TB8

Transmit Bit 8

Modes 0 and 1: Not used.

Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.

RB8

Receiver Bit 8

Mode 0: Not used.

Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.

Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received.

Transmit Interrupt Flag

Set by the transmitter after the last data bit is transmitted.

Must be cleared by software.

Receive Interrupt Flag

Set by the receiver after the stop bit of a frame has been received.

Must be cleared by software.

AT80SND2CMP3B Datasheet(PDF) 178 Page - ATMEL Corporation

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